“The evaluation of analog switches, multiplexers, operational amplifiers and other ICs poses a challenge for IC test engineers. A typical test requires applying a test voltage or forced voltage to the input of the device and measuring any resulting leakage current and offset current, which is often performed at the level of 1pA or lower. The low-power measurement circuit in Figure 1, Figure 2, and Figure 3 is in sharp contrast with the slow and expensive commercial automatic tester. This circuit can force a wide test voltage range and provide fast stability, enabling device test throughput The speed is at its highest.The widespread use of surface mount components reduces its printed circuit board space requirements
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The evaluation of analog switches, multiplexers, operational amplifiers and other ICs poses a challenge for IC test engineers. A typical test requires applying a test voltage or forced voltage to the input of the device and measuring any resulting leakage current and offset current, which is often performed at the level of 1pA or lower. The low-power measurement circuit in Figure 1, Figure 2, and Figure 3 is in sharp contrast with the slow and expensive commercial automatic tester. This circuit can force a wide test voltage range and provide fast stability, enabling device test throughput The speed is at its highest. The widespread use of surface mount components minimizes its printed circuit board space requirements and enables the packaging of multiple measurement circuits to be close to the test fixture.
This circuit includes forced voltage buffer/amplifier, floating rail power supply, IVC (current to voltage converter). Applying a forced voltage to the device under test causes leakage current, and the circuit converts the leakage current into an output voltage proportional to it. In conventional IVC, the current to be measured forms a voltage across the shunt resistor. IVC uses a feedback ammeter topology in which the operational amplifier IC1 is AD795 from Analog Devices, which subtracts the unknown current from the feedback current and provides an output voltage proportional to the unknown current (Figure 1).
In this design, the DC resistance of the input terminal mainly includes the effective input resistance of R2 and IC1, which is slightly larger than 100Ω under DC current. In the frequency range of 50Hz ~ 300Hz of the power line,
The average value of the AC impedance of the circuit is about 10 kΩ, which is one thousandth of the input resistance (about 10MΩ) of the typical shunt resistor IVC. The circuit’s 100MΩ feedback resistor R1 provides a current-to-voltage conversion ratio that is 10 times the shunt conversion ratio. The stabilization speed of this design is much faster than that of the shunt converter, and it can provide good interference suppression at the power line frequency. When testing the input current of the operational amplifier, it also reduces the unwanted voltage divider effect.
The current-to-voltage conversion ratio generated by R1 is 100mV/pA. The amplifier IC2 is AD795, which provides an additional voltage gain of 10, thereby increasing the ratio to 1mV/pA and reducing the influence of errors introduced by the CMRR (common-mode rejection ratio) of the differential amplifier IC3. The differential amplifier IC3 is OP1177, which subtracts the forced voltage from the output voltage of the IVC and provides a ground-referenced output signal.
A pair of back-to-back BAV199 diodes D1A and D1B shunt high current to the forced voltage amplifier IC4 and its protective fuse F1, thereby protecting IC1 from voltage overload. When the forced voltage changes rapidly from one value to another, these diodes provide high drive current during the high conversion rate interval, thereby greatly improving the IVC settling time.
A slightly compensated, high-voltage OPA551 amplifier IC4 with a gain of 3 operates on a ±30V power supply, and obtains a forced voltage of up to ±22V from an ordinary ±7V ATE (automatic test equipment) voltage (Figure 2). If the device under test is catastrophically short-circuited, the fuse F1 will limit the fault current from IC4 (which may bring a short-circuit current of up to 380mA), thereby preventing further damage.
The output of IC4 also drives a voltage regulator circuit, which generates a ±5V floating supply voltage, which is referenced to the test input forcing voltage (Figure 3). When using a ±30V power supply, this part of the circuit consumes less than 100mW of power. Vishay/Siliconix SST505 JFET constant current regulator “diodes” Q1 and Q4 provide a 1mA constant current source, which is buffered by transistors Q2 and Q3. Each stabilized diode carries a maximum rated voltage of 45V, and these buffers limit the voltage applied to the diode to approximately 3V, thereby providing overvoltage protection.
A current of 1mA is applied to resistors R5 and R6 to form a ±5V line voltage. Diodes D2 and D3 compensate the base-emitter voltage drop of emitter followers Q6B and Q7B. When the defective device under test short-circuits its power supply to the input node of the IVC, transistors Q6A and Q7A provide overvoltage protection. Transistors Q5 and Q8 shunt the current diode, thereby limiting the output current of the floating power supply. During abnormal start-up, diode D4 provides protection against the polarity inversion of the floating power line.
When working, the circuit provides 0.999V/nA output within ±4nA full-scale input range and 1GΩ effective transimpedance. The output offset of the circuit corresponds to approximately 143fA. When the forced voltage range of ±22V is exceeded, the floating power supply line voltage begins to saturate, the input CMRR limit of IC3 becomes obvious, and the output voltage of IVC becomes non-linear. Figure 4 shows that within the forced voltage range of ±20V, the current measurement error of the circuit from its no-load output is -31 fA/V. The differential amplifier composed of IC3, RN2, and RN3 achieves most of the gain of the circuit, and the low input bias current of IC1 helps to achieve very low offset errors. The average value of the output linearity in the ±20V forced voltage range is 111 fA pp.
The conversion rate capability of the circuit will vary considerably, but generally speaking, when D1 drives the device under test, the output will faithfully convert the entire 40V forced voltage in 100ms or less. Once the high conversion period is over, the IVC is no longer saturated, and its output becomes an exponential voltage with a time constant of 1ms. The output stabilized to 100fA in approximately 10.6ms. Under no-load conditions, the circuit consumes approximately 10.2mA (at ±30V power supply) or 400mA (at ±15V power supply). The layout of the prototype circuit occupies approximately 1.5 square inches on a single-sided printed circuit board, and if components are placed on both sides of the double-sided board, the area can be reduced to 1 square inch. In order to achieve the best performance, the layout must have a guard ring around the input terminals and all traces connected to pin 2 of IC1. The size of the circuit allows it to be placed on the device under test fixture, minimizes the lead length, and minimizes electromagnetic interference caused by the power cord. This circuit can measure current of only 1pA, but it can adapt to large currents by reducing the value of R1.
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