“The industry trend for future antenna design is to use phased arrays. This technology trend, coupled with time-to-market pressures, has resulted in shortened development times, creating a number of challenges for RF designers in the field of phased array systems.
“
By Peter Delos, Charles Frick and Michael Jones
Introduction
The industry trend for future antenna design is to use phased arrays. This technology trend, coupled with time-to-market pressures, has resulted in shortened development times, creating a number of challenges for RF designers in the field of phased array systems. Challenges associated with RF electronics include:
• Validate RF electronics in a multi-channel environment
• Verify synchronization and calibration across multiple channels
• Parallel software development and production hardware development
To address these industry challenges, new multi-channel RF-to-data development platforms have emerged. This development platform integrates software-configurable data converters, RF distribution, power conditioning and clocking to provide a 16-channel, S-band direct sampling solution.
Integrated RF Sampling High Speed Converter
The newly released high-speed converter integrates ADC, DAC and digital signal algorithm blocks on a single chip. MxFE shown in Figure 1™An example is the Quad 16-bit, 12 GSPS RF DAC and Quad 12-bit, 4 GSPS RF ADC, consisting of 4 ADCs, 4 DACs, multiple digital up/down converters, and Numerically Controlled Oscillators (NCOs) and Finite Impulse Response (FIR) digital filter. The sampling rate of the DAC is 12 GSPS and the sampling rate of the ADC is 4 GSPS. The analog bandwidth provides direct sampling and waveform generation in the S-band and into the low C-band.
Figure 1. AD9081 functional illustration.
The converters handle a wider range of RF spectrum bands and embed on-chip DSP functionality, enabling users to configure programmable filters and digital up-conversion and down-conversion blocks to meet specific RF signal bandwidth requirements. Implementing embedded processing in a dedicated chip can significantly reduce power compared to architectures that perform these functions in an FPGA. Freeing up valuable FPGA resources enables designers to use the FPGA more cost-effectively, or to allocate FPGA resources to higher-level system application processing.
16-Channel, Direct RF Sampling Development Platform (Quad MxFE)
The 16-channel, direct RF sampling development platform is shown in Figure 2, and its block diagram is shown in Figure 3. To illustrate their naming conventions: We name the integrated converter Mixed-Signal Front End (MxFE), and the 16-channel board containing 4 MxFEs as Quad MxFE. The 4 MxFEs each contain 4 DACs and 4 ADCs, so there are 16 transmit channels and 16 receive channels in total.
Figure 2. 16-Channel, Direct RF Sampling Development Platform (Quad MxFE).
Figure 3. Quad MxFE block diagram.
The RF section contains baluns, amplifiers and filters to simplify the RF interface. A low-pass filter is included on the transceiver channel to reject the DAC image, and the DAC output typically has a gain block. Two gain and gain controls are included on the receiver channel, as well as a bandpass filter for second-order Nyquist sampling. The filter uses Mini-Circuits’ 1206 filter size, so users can replace the filter to suit different applications.
Channel spacing is 600mils per transmitter/receiver pair, supporting X-band, half wavelength, monopole element grid spacing. At this size, the design shows that each unit digital beamforming system is compatible with frequencies up to the X-band. Where the quad MxFE directly generates the S-band, an additional single RF mixer can be added for X-band frequency operation.
It contains clock circuits, and all clocks use the same reference frequency. The PLL of each converter is phase-locked to the reference frequency and provides the AD9081 clock input. Includes test point injection option to evaluate alternate converter clock sources. The digital clock also uses the same reference frequency. A clock chip provides the AD9081 with the SYSREF signal for synchronization, provides the FPGA with the required clock signal, and provides the option to provide the AD9081 with a reference frequency to use the AD9081’s internal PLL.
Power distribution and regulation are shown in Figure 4. All required voltages are derived from a single 12 V input. The power distribution design consists of a combination of switching regulators followed by low-noise linear regulators to provide noise-sensitive analog voltages.
Figure 4. Four MxFE power distribution.
software control
Software, firmware, and FPGA code have been developed to enable platform control through higher-level processing languages. MATLAB®Scripting and GUI enable system engineers to develop models that can interface directly with hardware within the MATLAB environment. The MATLAB interface supports evaluating user-defined waveforms directly in hardware. The receive data capture interface supports user-specific receive data processing.
Both software and firmware are open source, similar to other ADI modules based on our new transceivers or converters.
in conclusion
The Quad MxFE RF-to-bit development platform enables a common prototyping environment. Its features include:
• Development platform for multi-channel synchronization across multiple converter ICs and boards.
• Validate multi-channel performance in an evaluation board environment before customers, rather than developing production designs with the sole purpose of testing multiple channels simultaneously.
• Highly integrated and functional, enabling simultaneous software development and hardware production.
• A complete reference design with all circuits related to high-speed converters, including RFI/O, clock and synchronization circuits, power distribution, and high-speed digital I/O routing.
This combination of features can eliminate the prototyping step in product development for multi-channel RF systems, allowing RF engineers to leverage existing implementations and focus on developing system solutions. The RF-to-Data Development Platform was originally planned to support phased array development. However, its versatility enables it to be used in multi-channel RF systems such as radar, EW, 5G and instrumentation applications. From this, a single hardware, multi-application platform has been developed, which can provide a truly software-defined multi-channel environment.
author
Peter Delos
Peter Delos is Technical Director for Analog Devices Aerospace and Defense in Greensboro, NC, USA. He received his bachelor’s degree in electrical engineering from Virginia Tech in 1990 and his master’s degree in electrical engineering from New Jersey Institute of Technology in 2004. Peter has over 25 years of industry experience. He has spent most of his career working on advanced RF/analog system architecture, PWB and IC design. He is currently focused on miniaturizing high performance receiver, waveform generator and frequency synthesizer designs for phased array applications.
Charles Frick
Charles (Chas) Frick is a Systems Applications Engineer in the Aerospace and Defense Group at Analog Devices in Greensboro, NC, USA. Before joining Analog Devices, Chas received two bachelor’s degrees in robotics and electrical engineering from Worcester Polytechnic Institute in 2016. Since joining Analog Devices in 2016, he has worked on various forms of internal and external customer projects involving PCB design, embedded C code, MATLAB GUI, Python test automation, motor control, and more. Outside of work, Chas enjoys fixing his Jeep Wrangler JLR in the garage, or playing in the Uwharrie National Forest (probably covered in mud) with his wife and shaggy little bulldog “Atlas”.
Michael Jones
Mike Jones is a Principal Electrical Design Engineer for Analog Devices Aerospace and Defense in Greensboro, NC, USA. He joined Analog Devices in 2016. From 2007 to 2016, he worked at General Electric Company in Wilmington, North Carolina, as a microwave photonics design engineer, developing microwave and optical solutions for the nuclear industry. He received his BS in Electrical Engineering and BS in Computer Engineering from North Carolina State University in 2004 and his MS in Electrical Engineering from North Carolina State University in 2006.
No comments:
Post a Comment
Note: Only a member of this blog may post a comment.