ADALM2000 experiment: emitter follower (BJT)

　　Target

The purpose of this experiment is to study a simple NPN emitter follower, sometimes referred to as a common collector configuration.

　　Material

·ADALM2000 Active Learning Module

·Solderless Breadboard

·Jumper

·A 2.2 kΩ resistor (RL)

·A small signal NPN transistor (Q1 uses 2N3904)

　　instruction

The breadboard connection is shown in Figure 2. The output of the arbitrary waveform generator W1 is connected to the base terminal of Q1. The oscilloscope input 1+ (single-ended) is also connected to the W1 output. The collector terminal is connected to the positive (Vp) power supply. The emitter terminal is connected to a 2.2 kΩ load resistor and oscilloscope input 2+ (single-ended). The other end of the load resistor is connected to the negative (Vn) power supply. To measure the input-output error, you can connect 2+ to the base of Q1 and 2– to the emitter to Display the difference between channel 2 of the oscilloscope.

Figure 1. Emitter follower

　Hardware setup

The waveform generator is configured as a 1 kHz sine wave with a peak-to-peak amplitude of 4 V and an offset of 0. The single-ended input (2+) of channel 2 of the oscilloscope is used to measure the emitter voltage. The oscilloscope is configured to connect to channel 1+ to display the AWG generator output. When measuring the input-output error, connect channel 2 of the oscilloscope to display the difference between 2+ and 2–.

Figure 2. Emitter follower breadboard circuit

　　Procedure steps

Configure the oscilloscope to capture multiple cycles of the two signals measured. The resulting waveform is shown in Figure 3.

Figure 3. Emitter follower waveform

The ideal value of the incremental gain (VOUT/VIN) of the emitter follower is 1, but it is always slightly less than 1. The gain is generally calculated by the following formula:

It can be seen from the formula that to obtain a gain close to 1, we can increase RL or decrease re. It can also be seen that re is a function of IE. When IE increases, re will decrease. In addition, it can be seen from the circuit that IE is related to RL. If RL increases, IE will decrease. In a simple resistive load emitter follower, these two effects cancel each other out. Therefore, to optimize the gain of the follower, we need to find a way to reduce re or increase RL without affecting the other party. If you look at the follower from another angle, because of the DC offset of the transistor VBE itself, the difference between the input and the output should be constant within the expected swing. Affected by a simple resistive load RL, the emission collector current IE will increase and decrease as the output swings up and down. Because VBE is an exponential function of IE, when the coefficient of variation of IE is 2, the variation range of VBE is about 18 mV (at room temperature). Taking the swing from +2 V to –2 V as an example, the minimum IE = 2 V/2.2 kΩ or 0.91 mA, and the maximum IE = 6 V/2.2 kΩ or 2.7 mA. The magnitude of the change in VBE is 28 mV. Based on these experimental results, we can improve the emitter follower from one aspect. In order to make the emitter current of the amplifier transistor constant, the current mirror in “ADALM2000 Experiment: BJT Current Mirror” is now used to replace the emitter load resistance. The current mirror can obtain a relatively constant current in a wide voltage range. This relatively constant current in the transistor causes the VBE to be quite constant. From another point of view, the extremely high output resistance in the current source can effectively increase RL, but re remains at the low value set for the current.

　　Improved emitter follower

　　Additional materials

A 3.2 kΩ resistor (connect 1 kΩ and 2.2 kΩ resistors in series)

A small signal NPN transistor (Q1 uses 2N3904)

Two small signal NPN transistors (Q2 and Q3 are both SSM2212) to achieve the best VBE matching

　　instruction

The breadboard connections are shown in Figure 4 and Figure 5.

Figure 4. Improved emitter follower

　　Hardware setup

The waveform generator is configured as a 100 Hz triangle wave with a peak-to-peak amplitude of 3 V and an offset of 0. The single-ended input (2+) of channel 2 of the oscilloscope is used to measure the voltage of the emitter of Q1. The oscilloscope is configured to connect to channel 1+ to display the AWG generator output. When measuring the input-output error, connect channel 2 of the oscilloscope to display the difference between 2+ and 2–.

Figure 5. Improved emitter follower breadboard circuit

　　Procedure steps

Configure the oscilloscope to capture multiple cycles of the two signals measured. The resulting waveform is shown in Figure 6.

Figure 6. Improved emitter follower waveform

Figure 7. Example of Excel chart of input-output error of resistance and current source load

　　Low offset follower

The follower circuit we discussed earlier has a built-in offset-VBE. The circuit used next uses the upward shift of the VBE of the PNP emitter follower to offset the downward shift of the VBE of the NPN emitter follower.

　　Material

· A 6.8 kΩ resistor

· A 10 kΩ resistor

· A 0.01 μF capacitor

·A small signal PNP transistor (Q1 uses 2N3906)

·Three small signal NPN transistors (Q2, Q3 and Q4 adopt 2N3904 or SSM2212)

　　instruction

The breadboard connections are shown in Figure 8 and Figure 9. The output of the function generator is connected to the base terminal of the PNP transistor Q1. The collector terminal of Q1 is connected to the diode NPN Q3, which is the input of the current mirror. The emitter terminal is connected to the resistor R1 and the base terminal of the NPN transistor Q2. The oscilloscope input 2+ is connected to the emitter of Q2 and the collector of Q4. The emitter sets of Q3 and Q4 are connected to the negative (Vn) power supply. In order to achieve the best transistor matching, Q3 and Q4 use SSM2212 NPN matching pair.

Figure 8. Low offset follower

　Hardware setup

The waveform generator is configured as a 1 kHz sine wave with a peak-to-peak amplitude of 4 V and an offset of 0. The oscilloscope input channel 2 is set to 500 mV/div.

Figure 9. Low offset follower breadboard circuit

　　Procedure steps

Configure the oscilloscope to capture multiple cycles of the two signals measured. The resulting waveform is shown in Figure 10.

Figure 10. Low-offset follower waveform

A problem arises when a simple emitter follower drives a capacitive load. Since the emitter current is only limited by β multiplied by the base current, which is provided by the signal source driving the base, the output rise time is relatively fast. The fall time may be much slower and will be limited by the emitter resistance or current source.

Balanced slew rate follower

　　Material

· Two 2.2 kΩ resistors

· A 10 kΩ resistor

· A 0.01 μF capacitor

·Three small signal PNP transistors (Q2, Q3 and Q4 adopt 2N3906 or SSM2220)

·Three small signal NPN transistors (Q1, Q5 and Q6 adopt 2N3904 or SSM2212)

　　instruction

The circuit shown in Figure 11 uses feedback to adjust the current in the emitter follower when the load current changes. The current drawn by the negative output can reach N (the gain of the NPN mirror) multiplied by the current of the PNP Q3. In order to achieve the best transistor matching, Q3 and Q4 use SSM2220 PNP matching pair, and Q5 and Q6 use SSM2212 NPN matching pair (NPN current mirror gain is 1). Add a second SSM2212 in parallel with Q5 (to increase the gain of the current mirror).

Figure 11. Balanced slew rate follower

　　Hardware setup

The waveform generator is configured as a 1 kHz sine wave with a peak-to-peak amplitude of 4 V and an offset of 0. The oscilloscope input channel 2 is set to 1 V/div.

Figure 12. Balanced slew rate follower breadboard circuit

　Procedure steps

Configure the oscilloscope to capture multiple cycles of the two signals measured. The resulting waveform is shown in Figure 13.

Figure 13. Balanced slew rate follower waveform

Another way to improve the emitter follower is to reduce the effective re through negative feedback. You can increase the negative feedback factor by increasing the open-loop gain by adding a second transistor to reduce re. The single transistor is replaced by a feedback pair, which provides 100% voltage feedback to the emitter set of the first transistor. This feedback pair is usually called a complementary feedback pair. The value of R2 determines whether an excellent linearity can be achieved, because it determines the IC of transistor Q1 and also determines the load on its collector.

　　Complementary feedback to emitter follower

Material

· A 2.2 kΩ resistor

· A 10 kΩ resistor

·A small signal NPN transistor (Q1 uses 2N3904)

·A small signal PNP transistor (Q2 uses 2N3906)

　　instruction

The breadboard connections are shown in Figure 14 and Figure 15.

Figure 14. Complementary feedback to emitter follower.

　　Hardware setup

The waveform generator is configured as a 1 kHz sine wave with a peak-to-peak amplitude of 2 V and an offset of 0. The oscilloscope input channel 2 is set to 1 V/div.

Procedure steps

Configure the oscilloscope to capture multiple cycles of the two signals measured. The resulting waveform is shown in Figure 16.

　　problem:

Can you give three characteristics of the emitter follower circuit?

You can find the answers to the questions on the student zone blog.

About the Author

Doug Mercer graduated from Rensselaer Polytechnic Institute (RPI) in 1977 with a bachelor’s degree in electrical engineering. Since joining ADI in 1977, he has directly or indirectly contributed more than 30 data converter products and holds 13 patents. He was appointed as an ADI researcher in 1995. In 2009, he transitioned from a full-time job and continued to serve as an ADI consultant as an honorary researcher, writing articles for the “Active Learning Program”. In 2016, he was appointed as the Resident Engineer of the RPI ECSE Department.

Antoniu Miclaus is currently a system application engineer at ADI, working on ADI teaching projects and developing embedded software for Circuits from the Lab®, QA automation and process management. He joined ADI in Cluj-Napoca, Romania in February 2017. He is currently a master of science student in the software engineering master program of Bebes Bowyer University and holds a bachelor’s degree in electronics and telecommunications engineering from Cluj-Napoca University of Technology.

　

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